IPC J-STD-012 CD-1996 倒装芯片和芯片规模技术的实施
Implementation of Flip Chip and Chip Scale Technology
IPC J-STD-012-1996 倒装芯片和芯片规模技术的实施
This document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include
Implementation of Flip Chip and Chip Scale Technology
IPC J-STD-013 CD-1996 倒装芯片和芯片规模技术的实施
Implementation of Flip Chip and Chip Scale Technology
SNI 01-4304-1996 凤梨芯片
Pineapples chips
SNI 01-4306-1996 红薯芯片
Sweet potatoes chips
IPC/EIA J-STD-028-1999 倒装芯片和芯片级凸块构造性能标准
This standard establishes the construction detail requirements for bumps and other terminal structures on flip chips and chip scale carriers. All flip
Performance Standard for Construction of Flip Chip and Chip Scale Bumps
IPC/EIA J-STD-028 CD-1999 倒装芯片和芯片级凸块构造性能标准
Performance Standard for Construction of Flip Chip and Chip Scale Bumps
ES 59008-5-1-2001 半导体芯片的数据要求第 5-1 部分：芯片类型的特殊要求和建议 裸芯片
Data Requirements for Semiconductor Die Part 5-1: Particular Requirements and Recommendations for Die Types - Bare Die
DS/ES 59008-5-1:2001 半导体芯片的数据要求 第 5-1 部分：芯片类型的特殊要求和建议 裸芯片
The European Specification specifies requirements for the exchange of data pertaining to bare semiconductor die, with or without connection structures
Data requirements for semiconductor die - Part 5-1: Particular requirements and recommendations for die types - Bare die
IPC J-STD-027-2003 倒装芯片和芯片尺寸配置的机械大纲标准
This standard establishes mechanical outline requirements for devices supplied in flip chip or Chip Size Package (CSP) formats, including die surface
Mechanical Outline Standard for Flip Chip and Chip Size Configurations
IPC J-STD-027 CD-2003 倒装芯片和芯片尺寸配置的机械外形标准
Mechanical Outline Standard for Flip Chip and Chip Size Configurations
JEDEC JESD22-B109-2002 倒装芯片张力
This test method is applicable to flip chip die after the die and substrate solder joint is formed, but prior to application of underfill or other
Flip Chip Tensile Pull
JEDEC JESD22-B109A-2009 倒装芯片拉力
Flip Chip Tensile Pull
JEDEC JESD22-B109B-2014 倒装芯片拉力
Flip Chip Tensile Pull
PAS 62084-1998 倒装芯片和芯片级技术的实施（1.0 版；替代品）
Implementation of Flip Chip and Chip Scale Technology (Edition 1.0; No Replacement)
IPC J-STD-012 CD-1996 倒装芯片和芯片规模技术的实施
Implementation of Flip Chip and Chip Scale Technology
IPC J-STD-012-1996 倒装芯片和芯片规模技术的实施
This document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include
Implementation of Flip Chip and Chip Scale Technology
IPC J-STD-013 CD-1996 倒装芯片和芯片规模技术的实施
Implementation of Flip Chip and Chip Scale Technology
SNI 01-4304-1996 凤梨芯片
Pineapples chips
SNI 01-4306-1996 红薯芯片
Sweet potatoes chips
IPC/EIA J-STD-028-1999 倒装芯片和芯片级凸块构造性能标准
This standard establishes the construction detail requirements for bumps and other terminal structures on flip chips and chip scale carriers. All flip
Performance Standard for Construction of Flip Chip and Chip Scale Bumps
IPC/EIA J-STD-028 CD-1999 倒装芯片和芯片级凸块构造性能标准
Performance Standard for Construction of Flip Chip and Chip Scale Bumps
ES 59008-5-1-2001 半导体芯片的数据要求第 5-1 部分：芯片类型的特殊要求和建议 裸芯片
Data Requirements for Semiconductor Die Part 5-1: Particular Requirements and Recommendations for Die Types - Bare Die
DS/ES 59008-5-1:2001 半导体芯片的数据要求 第 5-1 部分：芯片类型的特殊要求和建议 裸芯片
The European Specification specifies requirements for the exchange of data pertaining to bare semiconductor die, with or without connection structures
Data requirements for semiconductor die - Part 5-1: Particular requirements and recommendations for die types - Bare die
IPC J-STD-027-2003 倒装芯片和芯片尺寸配置的机械大纲标准
This standard establishes mechanical outline requirements for devices supplied in flip chip or Chip Size Package (CSP) formats, including die surface
Mechanical Outline Standard for Flip Chip and Chip Size Configurations
IPC J-STD-027 CD-2003 倒装芯片和芯片尺寸配置的机械外形标准
Mechanical Outline Standard for Flip Chip and Chip Size Configurations
JEDEC JESD22-B109-2002 倒装芯片张力
This test method is applicable to flip chip die after the die and substrate solder joint is formed, but prior to application of underfill or other
Flip Chip Tensile Pull
JEDEC JESD22-B109A-2009 倒装芯片拉力
Flip Chip Tensile Pull
JEDEC JESD22-B109B-2014 倒装芯片拉力
Flip Chip Tensile Pull
PAS 62084-1998 倒装芯片和芯片级技术的实施（1.0 版；替代品）
Implementation of Flip Chip and Chip Scale Technology (Edition 1.0; No Replacement)
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