GB/T 41033-2021 CMOS集成电路抗辐射加固设计要求
本文件规定了CMOS集成电路抗辐射(总剂量、单粒子)加固设计的流程、设计要求、建模仿真、验证试验要求。 本文件适用于基于体硅/SOICMOS工艺的数字集成电路、模拟集成电路和数模混合集成电路的抗辐射(总剂量、单粒子)加固设计
Design requirements of radiation hardening for CMOS IC
ARMY MIL-M-64034 VALID NOTICE 2-2013 微电路、同步器、命令输出（SCO）、B 类、单片、CMOS、集成电路
Microcircuit, Synchronizer, Command Output (SCO), Class B, Monolithic, CMOS, Integrated Circuit
BS EN 61523-2:2002 延迟计算和功率计算标准.CMOS集成电路子程序库.预布局延迟计算规范
This standard specifies the pre-layout delay calculation method for CMOS1 ASIC Libraries which contains cell based primitives and memories to be used
Delay and power calculation standards - Pre-layout delay calculation specification for CMOS ASIC libraries
JEDEC JESD12-4-1987 CMOS Semicustom集成电路性能参数的规范方法
The v o l t a g e waveform f o l l o w i n g a t r a n s i t i o n from low impedance t o high impedance is a s t r o n g f u n c t i o n of t h e l
Method of Specification of Performance Parameters for CMOS Semicustom Integrated Circuits
SP5.4.1-2017 CMOS/BiCMOS集成电路Latch-up Sensitivity Testing Latch-up Testing Device Level
This document defines procedures to characterize the latch-up sensitivity of integrated circuits triggered by fast transients. Purpose This document
Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing Device Level
GB/T 17572-1998 半导体器件 集成电路 第2部分;数字集成电路 第四篇 CMOS数字集成电路 4000B和4000UB系列族规范
IEC电子元器件质量评定体系遵循IEC章程并在IEC授权下工作。该体系的目的是确定质量评定程序，以这种方式使一个参加国按有关规范要求放行的电子元器件需进一步试验而为其他所有参加国同样接受。 本族规范是半导体器件的一系列空白详细规范之一，并应与下列IEC标准一起使用。747-10
Semiconductor devices--Integrated circuits. Part 2: Digital integrated circuits. Section four--Family specification for complementary MOS digital integrated circuits, series 4000B and 4000UB
GB/T 9424-1998 半导体器件 集成电路 第2部分;数字集成电路 第五篇 CMOS数字集成电路4000B和4000UB系列空白详细规范
IEC电子元器件质量评定体系遵循IEC章程并在IEC授权下工作。该体系的目的是确定质量评定程序，以这种方式使一个参加国按有关规范要求放行的电子元器件需进一步试验而为其他所有参加国同样接受。 本空白详细规范是半导体器件的一系列空白详细规范之一，并应与下列IEC标准一起使用
Semiconductor devices lntegrated circuits Part 2: Digital integrated circuits Section five--Blank detail specification for complementary MOS digital integrated circuits, series 4000B and 4000UB
SIS SS-CECC 90104-1991 系列规范．CMOS数字集成电路4000 B 和4000 UB系列
Family specification: C. MOS digital integratedcircuits Series 4000 B and 4000 UB
SIS SS CECC 90104-1982 系列规范．CMOS 数字集成电路 4000 B 和4000 UB系列
Family specif/cation: CMOS dig/tat integrated circuits - Series 4000 B and 4000 UB
SP5.4-2004 CMOS/BiCMOS 集成电路的闩锁灵敏度测试瞬态闩锁测试 – 组件级电源瞬态激励
Latch-Up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing – Component Level Supply Transient Stimulation
TR5.4-03-2011 静电放电灵敏度测试 CMOS/BiCMOS 集成电路的闩锁灵敏度测试 瞬态闩锁测试 组件级电源瞬态激励
This technical report describes a procedure for measuring latch-up sensitivity of integrated circuits to transients on power supply lines. Circuits
Electrostatic Discharge Sensitivity Testing Latch-Up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing – Component Level Supply Transient Stimulation
IEEE 1181-1991 CMOS 和 BiCMOS 集成电路工艺表征的闩锁测试方法的推荐实践
Recommended Practice for Latchup Test Methods for CMOS and BiCMOS Integrated-Circuit Process Characterization
IEEE Std 1181-1991 CMOS 和 BiCMOS 集成电路工艺特性的闩锁测试方法的 IEEE 推荐规程
Recommendations are provided for the layout and test methods required to characterize properly latchup behavior in CMOS and BiCMOS integrated circuit
IEEE Recommended Practice for Latchup Test Methods for CMOS and BiCMOS Integrated-Circuit Process Characterization
SJ 20758-1999 半导体集成电路CMOS门阵列器件规范
本规范规定了半导体集成电路CMOS型门阵列器件的详细要求。 本规范适用于器件的研制、生产和采购
Semiconductor integrated circuits Specification for COMS gate array devices
GB/T 3435-1987 半导体集成CMOS电路系列和品种 4000系列的品种
本标准规定了半导体集成CMOs电路4000系列品种（以下简称器件）的逻辑功能、引出端排列和主要电参数。器件的鉴定和质量评定应符合器件详细规范的规定
Series and products for semiconductor CMOS integrated circuits--Products of families 4000
GB/T 41033-2021 CMOS集成电路抗辐射加固设计要求
本文件规定了CMOS集成电路抗辐射(总剂量、单粒子)加固设计的流程、设计要求、建模仿真、验证试验要求。 本文件适用于基于体硅/SOICMOS工艺的数字集成电路、模拟集成电路和数模混合集成电路的抗辐射(总剂量、单粒子)加固设计
Design requirements of radiation hardening for CMOS IC
ARMY MIL-M-64034 VALID NOTICE 2-2013 微电路、同步器、命令输出（SCO）、B 类、单片、CMOS、集成电路
Microcircuit, Synchronizer, Command Output (SCO), Class B, Monolithic, CMOS, Integrated Circuit
BS EN 61523-2:2002 延迟计算和功率计算标准.CMOS集成电路子程序库.预布局延迟计算规范
This standard specifies the pre-layout delay calculation method for CMOS1 ASIC Libraries which contains cell based primitives and memories to be used
Delay and power calculation standards - Pre-layout delay calculation specification for CMOS ASIC libraries
JEDEC JESD12-4-1987 CMOS Semicustom集成电路性能参数的规范方法
The v o l t a g e waveform f o l l o w i n g a t r a n s i t i o n from low impedance t o high impedance is a s t r o n g f u n c t i o n of t h e l
Method of Specification of Performance Parameters for CMOS Semicustom Integrated Circuits
SP5.4.1-2017 CMOS/BiCMOS集成电路Latch-up Sensitivity Testing Latch-up Testing Device Level
This document defines procedures to characterize the latch-up sensitivity of integrated circuits triggered by fast transients. Purpose This document
Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing Device Level
GB/T 17572-1998 半导体器件 集成电路 第2部分;数字集成电路 第四篇 CMOS数字集成电路 4000B和4000UB系列族规范
IEC电子元器件质量评定体系遵循IEC章程并在IEC授权下工作。该体系的目的是确定质量评定程序，以这种方式使一个参加国按有关规范要求放行的电子元器件需进一步试验而为其他所有参加国同样接受。 本族规范是半导体器件的一系列空白详细规范之一，并应与下列IEC标准一起使用。747-10
Semiconductor devices--Integrated circuits. Part 2: Digital integrated circuits. Section four--Family specification for complementary MOS digital integrated circuits, series 4000B and 4000UB
GB/T 9424-1998 半导体器件 集成电路 第2部分;数字集成电路 第五篇 CMOS数字集成电路4000B和4000UB系列空白详细规范
IEC电子元器件质量评定体系遵循IEC章程并在IEC授权下工作。该体系的目的是确定质量评定程序，以这种方式使一个参加国按有关规范要求放行的电子元器件需进一步试验而为其他所有参加国同样接受。 本空白详细规范是半导体器件的一系列空白详细规范之一，并应与下列IEC标准一起使用
Semiconductor devices lntegrated circuits Part 2: Digital integrated circuits Section five--Blank detail specification for complementary MOS digital integrated circuits, series 4000B and 4000UB
SIS SS-CECC 90104-1991 系列规范．CMOS数字集成电路4000 B 和4000 UB系列
Family specification: C. MOS digital integratedcircuits Series 4000 B and 4000 UB
SIS SS CECC 90104-1982 系列规范．CMOS 数字集成电路 4000 B 和4000 UB系列
Family specif/cation: CMOS dig/tat integrated circuits - Series 4000 B and 4000 UB
SP5.4-2004 CMOS/BiCMOS 集成电路的闩锁灵敏度测试瞬态闩锁测试 – 组件级电源瞬态激励
Latch-Up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing – Component Level Supply Transient Stimulation
TR5.4-03-2011 静电放电灵敏度测试 CMOS/BiCMOS 集成电路的闩锁灵敏度测试 瞬态闩锁测试 组件级电源瞬态激励
This technical report describes a procedure for measuring latch-up sensitivity of integrated circuits to transients on power supply lines. Circuits
Electrostatic Discharge Sensitivity Testing Latch-Up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing – Component Level Supply Transient Stimulation
IEEE 1181-1991 CMOS 和 BiCMOS 集成电路工艺表征的闩锁测试方法的推荐实践
Recommended Practice for Latchup Test Methods for CMOS and BiCMOS Integrated-Circuit Process Characterization
IEEE Std 1181-1991 CMOS 和 BiCMOS 集成电路工艺特性的闩锁测试方法的 IEEE 推荐规程
Recommendations are provided for the layout and test methods required to characterize properly latchup behavior in CMOS and BiCMOS integrated circuit
IEEE Recommended Practice for Latchup Test Methods for CMOS and BiCMOS Integrated-Circuit Process Characterization
SJ 20758-1999 半导体集成电路CMOS门阵列器件规范
本规范规定了半导体集成电路CMOS型门阵列器件的详细要求。 本规范适用于器件的研制、生产和采购
Semiconductor integrated circuits Specification for COMS gate array devices
GB/T 3435-1987 半导体集成CMOS电路系列和品种 4000系列的品种
本标准规定了半导体集成CMOs电路4000系列品种（以下简称器件）的逻辑功能、引出端排列和主要电参数。器件的鉴定和质量评定应符合器件详细规范的规定
Series and products for semiconductor CMOS integrated circuits--Products of families 4000
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