IEEE Std 1181-1991 CMOS 和 BiCMOS 集成电路工艺特性的闩锁测试方法的 IEEE 推荐规程
Recommendations are provided for the layout and test methods required to characterize properly latchup behavior in CMOS and BiCMOS integrated circuit
IEEE Recommended Practice for Latchup Test Methods for CMOS and BiCMOS Integrated-Circuit Process Characterization
SP5.4-2004 CMOS/BiCMOS 集成电路的闩锁灵敏度测试瞬态闩锁测试 – 组件级电源瞬态激励
Latch-Up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing – Component Level Supply Transient Stimulation
TR5.4-03-2011 静电放电灵敏度测试 CMOS/BiCMOS 集成电路的闩锁灵敏度测试 瞬态闩锁测试 组件级电源瞬态激励
This technical report describes a procedure for measuring latch-up sensitivity of integrated circuits to transients on power supply lines. Circuits
Electrostatic Discharge Sensitivity Testing Latch-Up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing – Component Level Supply Transient Stimulation
IEEE 1181-1991 CMOS 和 BiCMOS 集成电路工艺表征的闩锁测试方法的推荐实践
Recommended Practice for Latchup Test Methods for CMOS and BiCMOS Integrated-Circuit Process Characterization
SJ 20954-2006 集成电路锁定试验
本标准规定了集成电路（IC）的电流锁定和过压锁定的试验方法。 本标准的目的是建立测试IC锁定试验的方法，用来判断集成电路锁定特性并确定锁定的失效判据。锁定敏感性对于决定产品可靠性、最小故障率（NTF）和过电应力失效（EOS）非常重要。 本试验方法适用于NMOS、CMOS
Integrated circuits latch-up test
JEDEC JESD78B-2008 IC闩锁测试
IC Latch-Up Test
JEDEC JESD78C-2010 IC闩锁测试
IC Latch-Up Test
JEDEC JESD78D-2011 IC闩锁测试
IC Latch-Up Test
JEDEC JESD78E-2016 IC闩锁测试
IC Latch-Up Test
GJB 9389-2018 集成电路锁定试验方法
Integrated circuit lock test method
DIN EN 15685:2019-10 建筑五金 - 要求和测试方法 - 多点锁、闩锁和锁定板 - 特性和测试方法
Building hardware - Requirements and test methods - Multipoint locks, latches and locking plates - Characteristics and test methods; German and English version prEN 15685:2019 / Note: Date of issue 2019-09-06
PAS 62181-2000 IC 闩锁测试（1.0 版）
IC Latch-Up Test (Edition 1.0)
TR5.4-04-2013 静电放电灵敏度测试瞬态闩锁测试
INTRODUCTION Definition Transient latch-up (TLU) is defined as a state in which a low-impedance path@ resulting from a transient overstress
Electrostatic Discharge Sensitivity Testing Transient Latch-up Testing
19/30396879 DC BS EN 15685 建筑硬件 要求和测试方法 多点锁、闩锁和锁定板 特性及测试方法
BS EN 15685. Building hardware. Requirements and test methods. Multipoint locks, latches and locking plates. Characteristics and test methods
TR5.4-02-2008 CMOS 闩锁敏感性的测定 瞬态闩锁 技术报告第 2 号
Determination of CMOS Latch-up Susceptibility - Transient Latch-up - Technical Report No. 2
IEEE Std 1181-1991 CMOS 和 BiCMOS 集成电路工艺特性的闩锁测试方法的 IEEE 推荐规程
Recommendations are provided for the layout and test methods required to characterize properly latchup behavior in CMOS and BiCMOS integrated circuit
IEEE Recommended Practice for Latchup Test Methods for CMOS and BiCMOS Integrated-Circuit Process Characterization
SP5.4-2004 CMOS/BiCMOS 集成电路的闩锁灵敏度测试瞬态闩锁测试 – 组件级电源瞬态激励
Latch-Up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing – Component Level Supply Transient Stimulation
TR5.4-03-2011 静电放电灵敏度测试 CMOS/BiCMOS 集成电路的闩锁灵敏度测试 瞬态闩锁测试 组件级电源瞬态激励
This technical report describes a procedure for measuring latch-up sensitivity of integrated circuits to transients on power supply lines. Circuits
Electrostatic Discharge Sensitivity Testing Latch-Up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing – Component Level Supply Transient Stimulation
IEEE 1181-1991 CMOS 和 BiCMOS 集成电路工艺表征的闩锁测试方法的推荐实践
Recommended Practice for Latchup Test Methods for CMOS and BiCMOS Integrated-Circuit Process Characterization
SJ 20954-2006 集成电路锁定试验
本标准规定了集成电路（IC）的电流锁定和过压锁定的试验方法。 本标准的目的是建立测试IC锁定试验的方法，用来判断集成电路锁定特性并确定锁定的失效判据。锁定敏感性对于决定产品可靠性、最小故障率（NTF）和过电应力失效（EOS）非常重要。 本试验方法适用于NMOS、CMOS
Integrated circuits latch-up test
JEDEC JESD78B-2008 IC闩锁测试
IC Latch-Up Test
JEDEC JESD78C-2010 IC闩锁测试
IC Latch-Up Test
JEDEC JESD78D-2011 IC闩锁测试
IC Latch-Up Test
JEDEC JESD78E-2016 IC闩锁测试
IC Latch-Up Test
GJB 9389-2018 集成电路锁定试验方法
Integrated circuit lock test method
DIN EN 15685:2019-10 建筑五金 - 要求和测试方法 - 多点锁、闩锁和锁定板 - 特性和测试方法
Building hardware - Requirements and test methods - Multipoint locks, latches and locking plates - Characteristics and test methods; German and English version prEN 15685:2019 / Note: Date of issue 2019-09-06
PAS 62181-2000 IC 闩锁测试（1.0 版）
IC Latch-Up Test (Edition 1.0)
TR5.4-04-2013 静电放电灵敏度测试瞬态闩锁测试
INTRODUCTION Definition Transient latch-up (TLU) is defined as a state in which a low-impedance path@ resulting from a transient overstress
Electrostatic Discharge Sensitivity Testing Transient Latch-up Testing
19/30396879 DC BS EN 15685 建筑硬件 要求和测试方法 多点锁、闩锁和锁定板 特性及测试方法
BS EN 15685. Building hardware. Requirements and test methods. Multipoint locks, latches and locking plates. Characteristics and test methods
TR5.4-02-2008 CMOS 闩锁敏感性的测定 瞬态闩锁 技术报告第 2 号
Determination of CMOS Latch-up Susceptibility - Transient Latch-up - Technical Report No. 2
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